1. Field of the Invention
The present invention relates to a semiconductor memory and, more particularly, relates to a pull-down circuit connected to a word line in a random access memory using a field effect transistor (simply referred to as a transistor hereinafter).
2. Description of the Prior Art
FIG. 1 shows a portion of a random access memory using a conventional word line pull-down circuit, in which two bits of memory cells each including a single transistor and a single capacitor per a bit, two decoders for selecting these memory cells, a sense amplifier for amplifying memory cell data and two pull-down circuits for two word lines are shown.
In FIG. 1, a memory cell 1 of a bit comprises a storage capacitor 2 for storing data of a logical "1" or "0" (in this specification "1" or "0" indicates a logical value), one end of the capacitor 2 being connected to a ground, and a switching transistor 3 having a first main electrode connected to the other end of the storage capacitor 2 and reading, writing or holding the data in the storage capacitor 2. The memory cell 1 further includes parasitic capacitance 4 associated with the transistor 3. A bit line 5 connected to a second main electrode of the switching transistor 3 transmits the data in the memory cell 1. A sense amplifier 6 for amplifying the cell data read out into the bit line 5 is shown. A signal .phi..sub.S for driving the sense amplifier 6 is applied to a terminal 7. A word line 8 is connected to the gate of the switching transistor 3 so that a signal for controlling ON and OFF of the switching transistor 3 is applied to the word line 8. Parasitic capacitance (9) is shown associated with the word line 8. A decoder circuit (10) for decoding address signals A1, A1, A2, A2, . . .An, An) applied for selecting the memory cell 1 includes terminals 11, . . .11 to which address signals are applied, transistors 12, . . .12 each connected to the corresponding terminal 11 for operating in response to the address signal, the respective transistors 12, . . .12 being connected in parallel with each other, and a charging transistor 14 having one main electrode connected to one end of each of the transistors 12 and for charging an output node 13 of the decoder circuit 10 which is a junction of one main electrode of the transistor 14 and one end of the transistor 12. The gate electrode of the charging transistor 14 is connected to a terminal 15 to which a charging signal .phi. is applied for controlling the charging transistor 14 and the other main electrode of the charging transistor 14 is connected to a terminal 16 to which a source voltage V is applied. A transistor 17 is connected between the word line 8 and a terminal 19 to which a clock signal .phi. is applied, the gate of the transistor 17 being connected to the output node 13 in the decoder 10. The transistor 17 couples the clock signal .phi. to the word line 8 in response to the level of the output node 13 in the decoder circuit 10. A capacitor 18 is connected between the output node 13 in the decoder circuit 10 and the word line 8. The capacitor 18 serves as capacitance for boosting the level at the time when the output node 13 in the decoder circuit 10 is "1" level and for transmitting the "1" level of the clock signal .phi. to the word line 8 without any drop because of a threshold voltage V.sub.TH of the transistor 17. A pull-down circuit 20 for grounding a voltage in a non-selected word line comprises a transistor 21 connected between the word line 8 and a ground, a transistor 22 crossed with the transistor 21, that is, having one main electrode (in this case, a drain) connected to the gate of the transistor 21 and the other main electrode (in this case, a source) connected to a ground and a gate connected to the word line 8 and a charging transistor 23 connected between a terminal 16 to which a source voltage V is applied and one main electrode of the transistor 22 and having a gate connected to a terminal 15 to which a clock signal .phi. is applied. The charging transistor 23 renders a transistor 21 conductive or ON to connect the word line 8 to a ground when the memory cell 1 is in a non-selected state. A decoder circuit 24 for selecting the same memory cell 28 as the above described memory cell 1 has the same structure as the above described decoder circuit 10 but has a different response to an address signal. Reference numeral 25 denotes an output node of the decoder circuit 24 and reference numeral 26 denotes a transistor connected between the terminal 19 to which a clock signal .phi. is applied and a word line 27 and operating in the same manner as the above described transistor 17. The transistor 26 couples the word line 27 of the memory cell 28 to the clock signal .phi. in response to the level of the output node 25 in the decoder circuit 24. The reference numeral 29 denotes a storage node in the memory cell 28, the reference numeral 30 denotes parasitic capacitance of the word line 27 and the reference numeral 31 denotes a pull-down circuit for the word line 27 which has the same structure as the above described pull-down circuit 20.
Now referring to waveforms of FIG. 2, an operation of a circuit in FIG. 1 will be described.
It is assumed herein that the data "0" is stored in the memory cell 1, the data "1" is stored in the memory cell 28 and now the data "0" stored in the memory cell 1 is going to be read out.
A period from the time t.sub.0 to t.sub.1 in FIG. 2 is a precharge period for the memory system. During the precharge period, the respective output nodes 13 and 25 of the decoder circuits 10 and 24 and the gates of the transistors 21 in the pull-down circuits 20 and 31 are precharged in response to the clock signal .phi.. Since the clock signal .phi. is a ground level of "0" at that time, the word lines 8 and 27 are grounded through the transistors 17 and 26 and the transistors 21 in the pull-down circuits, respectively. Accordingly, each switching transistor 3 in both memory cells 1 and 28 is in an OFF state and hence the cell data is in a holding state. If and when an address input is applied to the respective terminals 11 of the decoder circuits 10 and 24 at the time point t.sub.2 after the clock signal .phi. becomes "0" at the time point t.sub.1, the memory cell 1 is selected. As a result, the output node 25 in the decoder circuit 24 becomes "0" level through the transistor 12 and the output node 13 in the decoder circuit 10 is still held in the "1" level. Accordingly, the transistor 26 turns to the OFF state with the transistor 17 being held in the ON state. At that time, the word lines 8 and 27 are "0" since the clock signal .phi. is "0" level and each transistor 21 in the pull-down circuits 20 and 31 is in the ON state.
At the time point t.sub.3, the clock signal .phi. becomes "1" and hence the word line 8 is charged through the transistor 17. At that time, although the word line 8 is grounded by the transistor 21 in the pull-down circuit 20, the voltage in the word line 8 progressively increases with increase of the clock signal since the ON resistance in the transistor 17 is set to be smaller than the ON resistance of the transistor 21 in the pull-down circuit 20. Then, if and when the voltage in the word line 8 exceeds the threshold voltage V.sub.TH of the transistor 22, the transistor 22 is rendered conductive and the transistor 21 is rendered non-conductive or OFF, whereby the voltage in the word line 8 follows a variation of the clock signal .phi. and hence increases. As the voltage in the word line 8 increases, the output node 13 in the decode circuit 10 is boosted to over V+V.sub.TH through the bootstrap capacitance 18 in the decoder circuit 10 and hence the voltage in the word line 8 increases up to the "1" level (=V) of the clock signal .phi. without any drop of the amount of the threshold voltage of the transistor 17. On the other hand, since the transistor 26 is being in the OFF stage, the word line 27 is held to be grounded by the transistor 21. Then, the transistor 3 is rendered conductive in response to the voltage in the word line 8, so that the data "0" in the memory cell 1 is read out to the bit line 5. A variation of the voltage in the bit line at that time is shown in FIG. 2. More particularly, the word line 8 and the bit line 5 are coupled to each other by the parasitic capacitance 4 in the memory cell 1 and the voltage in the bit line 5 increases at the rising time of the word line 8 and thereafter gradually decreases in response to a read signal from the memory cell 1. If and when the clock signal .phi..sub.S is applied at the time point of t.sub.4, a fine amplitude of the voltage appearing in the bit line 5 is amplified by the sense amplifier 6 and the level of the bit line 5 becomes "0", that is, a ground level.
A reading out of the cell is completed at the time of t.sub.5 and the clock signal .phi. becomes "0". At the same time, the voltage in the word line 8 becomes "0". However, at that time the word line 8 and the bit line 5 are coupled to each other by the parasitic capacitance 4 in the memory cell 1 and thus the voltage in the bit line 5 is decreased. The voltage becomes less than -V.sub.TH as shown in FIG. 2. In case where the voltage is less than -V.sub.TH, which is equivalent to the state where a voltage more than the threshold voltage V.sub.TH of the switching transistor 3 in the memory cell 28 is applied between the gate (word line 27) and one main electrode (in this case, a source electrode)(bit line 5) in the switching transistor 3 in the memory cell 28, the switching transistor 3 is rendered conductive and hence the charge stored in the storage node 29 in the memory cell 28 is discharged through the switching transistor 3 so that the voltage in the storage node 29 is decreased (see .DELTA. V in FIG. 2). If the above described series of operations are repeated, the voltage in the storage node 29 in the memory cell 28 is gradually decreased and finally the data of "1" is changed to "0". In order to prevent this phenomenon, it would be preferred to make the threshold voltage in the switching transistor 3 larger so that the switching transistor 3 is made difficult to be rendered conductive . Nevertheless, if the threshold voltage is made larger, a voltage written into the memory cell becomes smaller by an amount of an increase of the threshold voltage. As a result, an inconvenience occurs where a signal level at the time of reading out of the data decreases.